崗位職責(zé):
1. Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
2. Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)
任職要求:
1. Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2. Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred.
3. CAD and script capability such as Python/Perl/Shell is preferred.
4. Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5. Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
6. Self-motivated and hard work.
- 電子技術(shù)·半導(dǎo)體·集成電路
- 200-499人
- 外商獨資·外企辦事處
- 浦口經(jīng)濟(jì)開發(fā)區(qū)紫峰路16號
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